Via holes formed by conventional etching techniques in silicon dioxide and sputtered quartz layers of semiconductor structures, have a cross-sectional configuration with sharp edge contours. The via hole in the layer of sputtered quartz will normally have a relatively sharp upper edge where the side walls meet the top surface of the layer. These sharp edges, particularly when combined with steep side wall surfaces, can lead to reduced thicknesses in metallized via pads and interconnection metallurgy stripes in a conductor stepdown, leading to conductor cracking, reducing the reliability of the semiconductor device.
The prior art has approached this problem by depositing the sputtered quartz layer to be etched, so as to have a varying etchable nature which changes in the thickness direction. The major portion of the layer, for example the bottom portion, is produced by conventional sputtering.
The top portion of the layer is deposited so that it will have a faster etch rate. This is accomplished by reducing the sputtering rate by varying the conditions within the sputtering apparatus. It has been found, however that the control of the variability of the etch rate of the sputtered quartz with thickness, cannot be uniformally maintained. Thus the inclination of the via hole wall produced by this prior art process, cannot be reliably made uniform from wafer to wafer or from batch to batch.